Technological Field
The present disclosure is related to semiconductor processing, in particular to the production of Through Semiconductor Vias for interconnecting stacked IC devices.
Description of the Related Technology
3D-integration of integrated circuit devices, hereafter also referred to as chips or semiconductor chips, produced on semiconductor wafers, has known many developments in recent years. The direct oxide-to-oxide bonding technique is one of the improvements which allows a very effective wafer bonding. It does however not result in electrical connections between both wafers or provide for external connections to both wafers. To make such connections, it is known in the present state of the art to produce at least two via-contacts (Through Si vias, TSVs or more generally referred to as Through Semiconductor Vias) from the backside of the stack, reaching contacts on the two wafers respectively. Connections are then realized by an additional interconnect, applied after bonding and TSV formation. Disadvantageously, such an additional interconnect increases the capacitance, resistance and inductance of the interconnect structure. Also, because of the tolerance of the wafer-to-wafer bonding technique, the landing pad on the bottom wafer has to be larger than the diameter of the minimum via size by at least two times the overlay tolerance of the wafer-to-wafer bonding plus two times the overlay accuracy of the backside lithography versus the stacked wafer pair fiducials. This results in relatively large via capture pads and limits achievable interconnect pitch.
U.S. Publication No. 20140264862 proposes the fabrication of a single TSV plug for contacting two stacked wafers. This is done by bonding two wafers, each comprising a substrate and an IMD (intermetal dielectric) portion comprising metal structures (bond pads, circuitry etc.), so that one intermetal dielectric is bonded to the other, thinning the top wafer, producing a first opening through the top wafer, producing a second opening through the IMD of the top wafer and partially through the 1 MB of the bottom wafer, while using metal structures in the top wafer as a hardmask, so that the single plug forms a connection between the circuitry of the top wafer's 1 MB and the bottom wafer's IMD. This production of two openings requires two lithography steps, which in turn requires large dimensions of the TSV diameter and of the metal contact structures in order to take into account the overlay accuracy of the two lithography steps.